1. Field of the Invention
The present invention relates to a sense amplifier control circuit and to a sense amplifier control method. More specifically, the invention relates to technology for controlling the activation of sense amplifiers in a dynamic random access memory (hereinafter referred to as DRAM) having a bank system.
2. Description of the Related Art
The trend toward higher operation speeds of arithmetic units (CPUs) has urged manufacturers to develop DRAM technology for transmitting data at high speeds.
In a conventional high-speed data processing and transmitting system, in general, a word line (WL) in the DRAM is activated by a row address strobe signal (hereinafter referred to as /RAS signal), and a sense amplifier activating signal activates the sense amplifier in synchronism with the /RAS signal after a suitable delay time by which the word line (WL) assumes a sufficiently large level due to the /RAS signal.
FIG. 12 is a block diagram explaining a circuit for executing a function for activating word lines (WL) in the DRAM and a function for activating sense amplifiers according to a prior art. In FIG. 12, the sense amplifier control circuit 100 is constituted by a /RAS signal processing circuit 1 that inputs a /RAS signal, a word line (WL) boost signal-generating circuit 2 which receives an output from the /RAS signal processing circuit 1 and outputs a control signal to a word line (WL) predecoder circuit 3 in response to the /RAS signal, a word line (WL) main decoder circuit 4 which receives an output from the word line (WL) predecoder circuit 3 and selects activation or de-activation of a predetermined word line (WL), a sense amplifier control signal-generating means 5 which generates a control signal for controlling the sense amplifier in response to the output of the word line (WL) boost signal-generating circuit 2, a bit line reset signal-generating circuit 6 that resets a bit line in response to an output of the sense amplifier control signal-generating means 5, and a sense amplifier drive signal-generating means 7 which outputs a sense amplifier activating signal. The basic operation of the sense amplifier control circuit 100 is as described below. That is, as shown in the waveform diagram of FIG. 13, the selected word line (WL) is activated at the down edge of the /RAS signal, and the sense amplifier drive signal-generating means 7 outputs an internal sense amplifier activating signal after the passage of a predetermined delay time that is set by taking into consideration the time by which the above word line (WL) is raised sufficiently to activate the sense amplifier.
In order to read the data in the sense amplifier, the bit line must have been reset prior to activating the word line (WL). Even in the prior art, therefore, a reset signal for resetting the bit line is output from the bit line reset signal-generating circuit 6 in synchronism with the break of the /RAS signal.
Then, as the /RAS signal rises, the word line (WL) is de-activated in synchronism therewith, and the sense amplifier is de-activated in synchronism therewith, whereby the bit line reset signal is no longer produced.
That is, according to the prior art, activation of the word line (WL) and activation of the sense amplifier are controlled by the same /RAS signal at all times. Therefore, when the /RAS signal is de-activated, both the word line (WL) and the sense amplifier are de-activated, and, hence, the data that is once selected is readily output in response to a suitable column address signal or is erased as the /RAS signal is de-activated. Even when it is desired to read related data, therefore, the row and column must be selected again using another /RAS signal, requiring extended periods of time for transmitting the data.
As the arithmetic units are operated at higher speeds, the above problem becomes important. When it is attempted to realize a high-speed DRAM technology, the above-mentioned conventional data transmission technology is no longer useful.